1. Field of the Invention
This invention generally relates to memory hardware for computer systems, and more specifically to memory expansion modules for expanding memory in computer systems.
2. Description of the Relevant Art
Many modern computer systems allow for memory expansion by way of single inline memory modules (SIMMs) and/or dual inline memory modules (DIMMs). SIMMs and DIMMs include small, compact circuit boards that are designed to mount easily into an expansion socket mounted on another circuit board, typically a computer motherboard. The circuit boards used to implement SIMMs and DIMMs include an edge connector comprising a plurality of contact pads, with contact pads typically being present on both sides of the circuit board. On SIMMs, opposing contact pads are connected together (i.e. shorted), and thus carry the same signal, while at least some opposing contact pads on DIMMs are not connected, and thus allowing different signals to be carried. Due to this, higher signal density may be accommodated by DIMMs.
Memory elements mounted on SIMMs and DIMMs are typically Dynamic Random Access Memory (DRAM) chips. DRAM chips store information as a charge on a capacitor, with the charge level representing a logic one or logic zero. Since a capacitor charge will dissipate over time, DRAM chips require refresh cycles on a periodic basis.
To access a location in a DRAM, an address must first be applied to the address inputs. This address is then decoded, and data from the given address is accessed. In modern DRAMs, rows and columns are addressed separately using row address strobe (RAS) and column address strobe (CAS) control signals. By using RAS and CAS signals, row and column addresses can be time-multiplexed on common signal lines, contact pads, and pins of the address bus. This allows a greater number of memory locations that can be addressed without a corresponding increase in the number of required signal lines, contact pads, and pins.
To address a memory location in a DRAM as described above, a RAS signal is asserted on the RAS input of the DRAM, and a row address is forwarded to row decode logic on a memory chip. The contents of all locations in the addressed row will then be sent to a column decoder, which is typically a combination multiplexer/demultiplexer. After row addressing is complete, a CAS signal is asserted, and a column address is sent to the column decoder. The multiplexer in the column decoder will then select the corresponding column from the addressed row, and the data from that specific row/column address is placed on the data bus for used by the computer system.
Although the RAS and CAS signals allow the time-multiplexing of address signals, total memory capacity in a system may be limited by the number of address inputs on the memory chips employed in the system. This is true even if the system address bus is wider than the number of address inputs for an individual memory chip. The use of memory chips with a greater number of address inputs, and hence higher capacity, may disproportionately increase the cost of the desired memory expansion. It would be desirable to increase the memory capacity for such a computer system by adding extra banks of memory without having to change the type of memory chip employed. However, the number of address inputs to the system""s memory chips limits the ability to do this. Furthermore, the presence of only one RAS and one CAS signal also limits the ability to expand system memory, as a separate bank of memory typically requires at minimum either a unique RAS or unique CAS signal for each bank. As such, it would be desirable to overcome the limitations described above in order to allow extra banks of memory to be added to a computer system, thereby expanding system memory capacity.
The problems outlined above may in large part be solved by a memory expansion module including multiple memory banks and a bank control circuit in accordance with the present invention. In one embodiment, a memory module includes a printed circuit board with a connector edge adapted for insertion in an expansion socket of a computer system. Mounted upon the circuit board is a plurality of memory chips, typically Dynamic Random Access Memory (DRAM) chips, which make up an upper bank and a lower bank of memory. A buffer circuit is mounted upon the printed circuit board, for the purpose of driving address signals, Column Address Strobe (CAS) signals, and write enable signals to each of the memory chips. Also mounted on the printed circuit board is a bank control circuit, which is coupled to the memory chips. An address signal is used as a bank selection input to the bank control circuit, which will drive Row Address Strobe (RAS) signals to the memory chips of the selected memory bank. The bank control circuit is further configured to drive RAS signals to both banks simultaneously during CBR (CAS before RAS) refresh operations, which occur when a CAS signal is asserted before a RAS signal. By using the bank control circuit to enable the addition of a second memory bank, a memory expansion can be realized without the need for higher capacity memory chips, which may result in an advantageous cost savings.
In one embodiment of the invention, a Dual Inline Memory Module (DIMM) employs a bank control circuit for bank selection. In this embodiment, the bank control circuit is a programmable logic device (PLD), although this circuit may be implemented in other forms for different embodiments. The bank control circuit receives a RAS signal, a CAS signal, and the selected address bit from expansion socket of a computer system. The bank control circuit drives multiple RAS signals. When the bank control circuit is in an idle state, receiving a RAS signal will cause a memory access operation to begin. The bank of memory to be selected will depend on the logic level of the address input to the bank control circuit. The bank control circuit will then drive RAS signals to the selected memory bank, allowing a row address to be selected. When the memory chips of the selected bank receive a CAS signal, the column address is selected, and the requested memory address is accessed.
If, when in an idle state, the bank control circuit receives a CAS signal, a CBR refresh cycle is begun. The CAS signal is received by both the bank control circuit and a buffer circuit, which drives CAS signals to each of the memory chips. Following this, a RAS signal is received by the bank control circuit, which then drives RAS signals to each of the DRAM chips of the memory module, and the CBR refresh is performed. When both the CAS and RAS inputs to the memory module are deasserted, the bank control circuit returns to an idle state.
Thus, in various embodiments, the memory expansion module with multiple memory banks and a bank control circuit advantageously allows greater memory capacity by accommodating multiple memory banks. Additionally, memory capacity can be increased without requiring the use of memory chips with a higher address width.